1. Field of the Invention
The present invention relates to the designing of masks to be used to manufacture integrated circuits. More specifically, the present invention relates to a method for improving the design of such masks.
2. Discussion of the Related Art
To manufacture integrated electronic circuits, a set of several masks comprising openings defining work areas on the circuit is used. For example, different masks may be successively used to define locations of dopant implantation, of etching, etc.
The manufacturing of the different masks necessary to obtain an integrated circuit implies a relatively high cost. Further, modern integrated circuits may require, for their production, several tens of masks. It is thus essential to properly test the mask generation files before launching the production of the masks, or even the production of the integrated circuits. Especially, the compatibility of the masks, for example, for their superposition, should be optimal. Having to redesign a set of masks, at the last minute before the launching of the production of integrated circuits or after the launching of the production, may imply very large manufacturing delays and costs.
For each electronic component technology, integrated circuit designers should comply with a number of design rules put together in a “Design Rules Manual”, or DRM. Such a manual gathers, among other things, sets of rules relative to the superposition or to the juxtaposition of the layers necessary for the forming of the electronic components.
FIG. 1 illustrates a few examples of rules that may be imposed on designers for the forming of integrated circuits. This drawing shows, in hatchings, different areas at the surface of a substrate intended to receive electronic components. Among the rules to be respected for electronic components, the following can be mentioned:                respecting a minimum width W of some elements of the components, for example, the width of MOS transistor gates, the length of a transistor channel;        respecting a minimum space S between different elements, to avoid interferences between these elements, for example, between two metal tracks, or again leakage currents;        respecting a minimum surface area A for some elements.        
FIG. 2 illustrates rules that may be imposed by DRMs when several layers are used to form electronic components, at close or superposed locations of a circuit. This drawing shows the design levels from which are formed masks which will subsequently be necessary to the manufacturing of electronic components, LAYER1 for which the contour of the openings is shown in full lines, and LAYER2 having its openings shown in hatched portions.
The examples of rules to be respected may be:                respecting a minimum enclosure E between the edge of the openings of the second mask LAYER2 and the edge of the openings of the first mask LAYER1. This, for example, corresponds to the case of electronic components formed in a well of a specific conductivity type. In this case, for their proper operation, the components should not be formed too close to the edge of the well. This may also correspond to elements which should be formed in superposed fashion: for example, a transistor gate above a well of a specific conductivity type.        respecting a minimum distance D between elements formed by means of second mask LAYER2 with respect to elements formed by means of first mask LAYER1. This, for example, corresponds to the case where the first mask defines a well of a given conductivity type and where the components formed at the level of the openings of the second mask should not be formed too close to this well due to a risk of interactions.        
It should be noted that the rules imposed by DRMs may also integrate an alignment error margin to take into account inaccuracies in the mask alignment on manufacturing of the circuits. The rules imposed by DRMs thus eliminate a number of situations with critical sizings, which could not operate properly and which are thus not accessible to designers.
Once the integrated circuits have been designed by the designers, the obtained CAD files should be turned into image files of the masks which will be necessary to form the integrated circuits. To achieve this, logical operations are defined by technologists to be applied to the integrated circuit files.
The logical operations also define all the elements missing for the proper operation of the circuit, which are not available to designers. Indeed, for an easy design of integrated circuits, designers only define some of the elements necessary to the forming of the integrated circuit. For example, in the case of a MOS transistor, designers may define the location of a well of a given conductivity type, and a second well necessary to the proper operation of the transistor may be automatically generated by the logical operations.
The logical operations finally define an optimized shape of the different masks. They may in particular provide to slightly widen the openings formed in the masks to compensate for a possible subsequent narrowing when the mask is being used.
FIG. 3 shows a conventional flowchart of the steps carried out to design integrated circuits, until the manufacturing of the masks used for manufacturing the integrated circuits.
As described hereabove, a first step 10 comprises forming a computer file which is an image of the desired integrated circuit (DESIGN FILE). This file is formed by designers 12 (DESIGNER), in compliance with the rules imposed by integrated circuit DRMs 14 associated with the technology used.
The integrated circuit file is then transformed, by a computer system, at a step 16 (LOP, Logical Operation Processing) and by means of a set of logical operations 18 (LO), to obtain an image file of the masks necessary to manufacture integrated circuits 20 (MASK FILES). The logical operations are especially provided to gather, within a same mask, the regions of the electronic components of the integrated circuits requiring a same processing.
As an example, low-voltage MOS transistors, high-voltage MOS transistors, dual-gate transistors, etc. may be provided on a same integrated circuit. Each of these transistors requires, to be formed, a specific processing, often obtained by a mask differentiation, for example, to form the wells of these different transistors. The logical operations of step 18 are used to generate the right masks according to the different steps to be carried out.
Step 16 of transformation of integrated circuit file 10 into a mask file may return errors, for example, in the case where the density of electronic components on the circuit would be too high, or in the case where there would be an incompatibility with the integrated circuit design rule manual. In this case, it is necessary to revise the transformation formulas 18 (LO) applied in transformation step 16 to validate or invalidate certain configurations provided by the designers.
Once step 18 has been carried out, all masks 20 are visually verified by a technologist (to spot evident errors, for example, of superposition of elements which should not be superposed), then is tested statistically again, at a step 22 (PLC) before the mask production. This last test, performed by a computer system, is a dimensional verification of the generated masks, for example, in comparison with dimensional criteria imposed by mask manufacturers (MRC, Manufacturing Rule Check), or with criteria imposed by integrated circuit manufacturers (PLC, Post Logical Check).
If test step 22 generates errors, a step 24 (ERROR) is provided, to modify logical operations 18 of transformation of step 20 so that the masks fulfill the conditions imposed by the mask manufacturers. This modification step is carried out manually by technologists and may be relatively long. Indeed, among all logical operations, the one having caused the incompatibility with the dimensional criteria imposed by the mask manufacturers should be targeted, and the required operation(s) should then be eliminated.
Once logical operations 18 have been modified, the operation of transformation of the integrated circuit file into a mask file is applied again to the integrated circuit file provided by the designers. If an error still occurs after test step 22, logical operations 18 are modified again and the transformation operation of step 16 is repeated as many times as necessary.
When test step 22 is validated, the masks are sent to production at a step 26 (MASK FAB) and the integrated circuit production may start.
A problem may arise in specific cases where the designers desire to integrate new components in the integrated circuits. “New component” here means an entirely new component or a new adaptation of a known component, for example, the adding of a doped region at a new location of a transistor, the modification of the dimensions of an insulated gate, etc.
When a new component is designed, the integrated circuit in which this component is provided may be transformed according to the method described in relation with FIG. 3 to obtain the set of masks corresponding to this circuit, if this set of masks can be generated with no error. It is generally provided, before performing this transformation, to form a test file in which many configurations of the new component, in interaction with other components, are gathered. This test file is then tested to see if it complies with the rules imposed by the DRMs, after which it is transformed by means of the logical operations. This enables to verify that this new component poses no problem, related to the DRMs, of integration into the desired integrated circuit, but also into other future configurations that may be given thereto.
However, it is possible to have a test circuit comprising new components complying with the conditions imposed by the DRMs, where the transformations of the logical operations pose no problem, with a good post-transformation test regarding the criteria of mask manufacturers, but with finally produced masks which do not provide high-quality components.
This may be due to the fact that the logical operations transforming the integrated circuit file into a mask file may incorrectly process the design of the new component, or may introduce errors during the transformation.
If an erroneous set of masks is used to produce integrated circuits, this may have significant consequences in terms of time and cost, especially if an entire new set of masks has to be designed and manufactured.
It thus cannot be envisaged to detect errors at the end of the mask manufacturing process. A method for limiting as much as possible the need to redesign integrated circuit masks is thus needed.